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Resist Development

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Future generations of computer chips will be manufactured with stringent requirements on three parameters: Resolution, Sensitivity, and Line Edge Roughness (LER). All three must be met and balanced, or the chips cannot be made. The following table summarizes the goals for each as laid out in the 2007 ITRS Roadmap:

Year Resolution LER Sensitivity
2013 32-nm half pitch (21-nm iso) 1.2 nm 10 mJ/cm2
2016 22-nm half pitch (15-nm iso) 0.8 nm 10 mJ/cm2
2019 16-nm half pitch (11-nm iso) 0.6 nm 10 mJ/cm2
24 nm HP 22 nm HP 20 nm HP
Resist C
12.7 mJ/cm2
 24 nm 22 nm 20 nm
Resist D
15.2 mJ/cm2
 24 nm 22 nm 20 nm
The Berkeley MET tool has been instrumental in improving resists so that resolution is now approaching 20 nm HP using 50 nm thick resists
45 nm HP 40 nm HP 35 nm HP 30 nm HP
1:1 45 nm 40 nm 35 nm Resist E
80-nm film
thickness
1:1.5 45 nm 40 nm 35 nm 30 nm
Contacts have also been printed 30 nm across at a variety of half-pitches
Further demonstrations of high pattern fidelity at small feature sizes
24 nm HP 22 nm HP 20 nm HP
24 nm 22 nm 20 nm
30 nm 1:1
contacts
 30 nm contacts cross section 30 nm contacts cross section
Year 40 nm Half-pitch 36 nm Half-pitch 32 nm Half-pitch Annular
Illumination
2006 40 nm 2006 16% 200nm DOF
2007 40 nm 2007 36 nm 2007 15% EL 200 nm DOF
2008 40 nm 2008 36 nm 2008 32 nm 2008 8% EL 150 nm DOF
Line-space resolution: Progress over Time (Click to see full-size images)

To characterize the performance of resists, systematic contact and corner resist blur metrics have been developed. Steady improvements in resist performance can be seen by comparing these metrics over time:
Contact and corner blur metrics over time

In contrast to the impressive improvements in resolution, line edge roughness (LER) remains the most difficult challenge facing EUV resists. This can be visualized by comparing LER to sensitivity for various resists to the target of LER < 1.2 nm at 5 mJ/cm2 on 32 nm dense nodes:
LER vs sensitivity for various EUV resists